{"id":1689,"date":"2024-11-18T11:44:18","date_gmt":"2024-11-18T11:44:18","guid":{"rendered":"https:\/\/nas01.tallpaul.net\/wordpress\/?p=1689"},"modified":"2024-11-18T15:04:18","modified_gmt":"2024-11-18T15:04:18","slug":"power-memory","status":"publish","type":"post","link":"https:\/\/nas01.tallpaul.net\/wordpress\/2024\/11\/power-memory\/","title":{"rendered":"IBM Power&#8217;s Revolutionary Approach to the Memory Era: Leading the Future of Enterprise Computing"},"content":{"rendered":"\n<p>In a groundbreaking presentation at the IBM TechXchange 2024, <a href=\"https:\/\/www.linkedin.com\/in\/bill-starke-3951814a\/\" target=\"_blank\" rel=\"noreferrer noopener\">William Starke<\/a>, IBM Distinguished Engineer and POWER Processor Chief Architect unveiled how IBM Power is pioneering the next major era in computing: the Memory Era. This shift comes at a crucial time when memory capabilities are becoming increasingly critical for enterprise computing and AI workloads.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">The Evolution of Computing Eras<\/h2>\n\n\n\n<p>Computing has progressed through distinct eras, each characterized by challenges and innovations. From the Clock Speed Era of the 1980s through 2007, when processors reached speeds of 5+ GHz, to the Multi-core Era, which brought us processors with 100+ cores, we&#8217;ve now entered what many consider the Memory Era. This transition comes at a crucial time when memory capabilities are becoming increasingly critical for enterprise computing and AI workloads.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Understanding the Computing-Memory Gap Crisis<\/h2>\n\n\n\n<p>Over the past two decades, computing power has experienced exponential growth:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>100x increase in transistors per processor chip<\/li>\n\n\n\n<li>112x improvement in rPerf (relative performance) scores<\/li>\n\n\n\n<li>140x growth in CPW (Commercial Processing Workload) scores<\/li>\n<\/ul>\n\n\n\n<p>However, traditional DDR DRAM bandwidth has only managed a 28x increase per unit of processor edge area, achieved through:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>16x improvement in DDR signalling speed (from 200 MHz to 3200 MHz)<\/li>\n\n\n\n<li>1.75x increase in solder ball density (from 29 to 51 signals per mm\u00b2)<\/li>\n\n\n\n<li>This growing disparity between computing power and memory capabilities has created a significant bottleneck in system performance.<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Current Industry Approaches and Their Limitations<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Direct Attach Memory<\/h3>\n\n\n\n<p>The typical industry approach uses direct-attach DDR memory, which faces several challenges:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Limited bandwidth due to signal integrity issues<\/li>\n\n\n\n<li>Poor reliability with signal-ended signaling<\/li>\n\n\n\n<li>Inefficient use of processor chip edge area<\/li>\n\n\n\n<li>Memory locked to specific DDR vintages<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">CXL Far Tier Memory<\/h3>\n\n\n\n<p>While intended for new storage class memory technologies, CXL (Compute Express Link) has been repurposed to address DDR4 obsolescence:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Higher latency compared to main memory<\/li>\n\n\n\n<li>Limited bandwidth<\/li>\n\n\n\n<li>Complexity in managing hybrid memory systems<\/li>\n\n\n\n<li>Primarily serving as a solution for recycling older DDR4 memory<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">HBM (High Bandwidth Memory)<\/h3>\n\n\n\n<p>Used primarily with accelerators like GPUs:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Extremely high bandwidth but very limited capacity<\/li>\n\n\n\n<li>Reliability concerns<\/li>\n\n\n\n<li>Rigid attachment limiting flexibility<\/li>\n\n\n\n<li>Expensive and complex packaging requirements<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">IBM Power&#8217;s Revolutionary Solution<\/h2>\n\n\n\n<p>IBM&#8217;s approach revolutionizes server memory architecture through Hierarchical Buffered Memory with OMI (OpenCAPI Memory Interface).<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Technical Innovations<\/h3>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Advanced Signaling Technology\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp;Differential, ultra-high bandwidth signalling<\/li>\n\n\n\n<li>&nbsp;&nbsp;Packetized, replayable, and steerable communications<\/li>\n\n\n\n<li>&nbsp;&nbsp;High-level OMI semantics ensuring signal integrity<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Buffer Architecture\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp;DDR controller integrated into a buffer<\/li>\n\n\n\n<li>&nbsp;&nbsp;Dual-port fan-out for improved bandwidth<\/li>\n\n\n\n<li>&nbsp;&nbsp;Contained DDR signalling within DIMM<\/li>\n\n\n\n<li>&nbsp;&nbsp;Spare DRAMs for enhanced reliability<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Historical Evolution\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp;Late 1990s-2010s: Good latency with puppet-string buffers<\/li>\n\n\n\n<li>&nbsp;&nbsp;2014: Centaur Agnostic Buffer introducing better latency<\/li>\n\n\n\n<li>&nbsp;&nbsp;2021: OMI Buffer achieving best latency (less than 10ns adder beyond DDR direct)<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n\n<h3 class=\"wp-block-heading\">Quantifiable Advantages<\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>4x higher bandwidth compared to traditional solutions<\/li>\n\n\n\n<li>4x greater memory capacity per processor<\/li>\n\n\n\n<li>9x more efficient use of processor chip edge area<\/li>\n\n\n\n<li>156x growth in memory bandwidth since POWER4 with OMI DDR5<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Key Differentiators<\/h3>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Technology Agnostic Design\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp; Memory and processors can be upgraded independently<\/li>\n\n\n\n<li>&nbsp;&nbsp; Future-proof architecture accommodating new memory technologies<\/li>\n\n\n\n<li>&nbsp;&nbsp; No lock-in to specific DDR generations<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Superior Reliability\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp; ECC protection<\/li>\n\n\n\n<li>&nbsp;&nbsp; Differential signalling<\/li>\n\n\n\n<li>&nbsp;&nbsp; Spare DRAM support<\/li>\n\n\n\n<li>&nbsp;&nbsp; Contained DDR signals within DIMM<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Scalability and Composability\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp; Flexible architecture supporting various configurations<\/li>\n\n\n\n<li>&nbsp;&nbsp; Efficient scaling for large memory deployments &nbsp;&nbsp; <\/li>\n\n\n\n<li>Better resource utilization through memory disaggregation<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n\n<h2 class=\"wp-block-heading\">Impact on Enterprise Computing and AI<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Enterprise Applications<\/h3>\n\n\n\n<p>The architecture is particularly beneficial for memory-intensive applications like SAP HANA, where:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>High memory bandwidth is crucial for real-time analytics<\/li>\n\n\n\n<li>Large memory capacity enables bigger in-memory databases<\/li>\n\n\n\n<li>Reliability is essential for business-critical operations<\/li>\n\n\n\n<li>Composable scale allows for flexible resource allocation<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">AI Workloads<\/h3>\n\n\n\n<p>As AI models continue to grow, IBM&#8217;s solution offers unique advantages:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Combined high bandwidth and capacity supporting larger models<\/li>\n\n\n\n<li>Efficient memory hierarchy for AI training and inference<\/li>\n\n\n\n<li>Flexible architecture accommodating evolving AI requirements<\/li>\n\n\n\n<li>Cost-effective scaling compared to HBM-only solutions<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Future Outlook<\/h2>\n\n\n\n<p>IBM Power&#8217;s memory architecture positions it as a leader in the Memory Era, particularly for:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Enterprise Computing\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp;Growing demand for in-memory databases<\/li>\n\n\n\n<li>&nbsp;&nbsp;Real-time analytics requirements<\/li>\n\n\n\n<li>&nbsp;&nbsp;Mission-critical reliability needs<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>AI and Machine Learning\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp;Expanding model sizes<\/li>\n\n\n\n<li>&nbsp;&nbsp;Increasing memory bandwidth requirements<\/li>\n\n\n\n<li>&nbsp;&nbsp;Need for flexible scaling<\/li>\n<\/ul>\n<\/li>\n\n\n\n<li>Hybrid Workloads\n<ul class=\"wp-block-list\">\n<li>&nbsp;&nbsp;Combined traditional and AI workloads<\/li>\n\n\n\n<li>&nbsp;&nbsp;Dynamic resource allocation &nbsp;&nbsp; &#8211; Varied performance requirements<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n\n<h2 class=\"wp-block-heading\">Conclusion<\/h2>\n\n\n\n<p>As we progress deeper into the Memory Era, IBM Power&#8217;s innovative approach to memory architecture provides a compelling solution to the growing computing-memory gap. While competitors struggle with hybrid solutions combining various technologies, IBM&#8217;s unified approach through OMI offers a cleaner, more efficient, and more scalable solution. This technological advantage becomes crucial for next-generation applications requiring high memory bandwidth, capacity, reliability, and composable scale. The success of this architecture validates IBM&#8217;s long-term vision and investment in memory technology, positioning IBM Power Systems as the platform of choice for future enterprise computing and AI workloads.<\/p>\n\n\n\n<ul class=\"wp-block-social-links aligncenter has-huge-icon-size has-icon-color is-style-default is-layout-flex wp-block-social-links-is-layout-flex\"><li style=\"color: #ffffff; \" class=\"wp-social-link wp-social-link-wordpress  wp-block-social-link\"><a rel=\"noopener nofollow\" target=\"_blank\" href=\"https:\/\/nas01.tallpaul.net\/wordpress\/\" class=\"wp-block-social-link-anchor\"><svg width=\"24\" height=\"24\" viewBox=\"0 0 24 24\" version=\"1.1\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" aria-hidden=\"true\" focusable=\"false\"><path d=\"M12.158,12.786L9.46,20.625c0.806,0.237,1.657,0.366,2.54,0.366c1.047,0,2.051-0.181,2.986-0.51 c-0.024-0.038-0.046-0.079-0.065-0.124L12.158,12.786z M3.009,12c0,3.559,2.068,6.634,5.067,8.092L3.788,8.341 C3.289,9.459,3.009,10.696,3.009,12z M18.069,11.546c0-1.112-0.399-1.881-0.741-2.48c-0.456-0.741-0.883-1.368-0.883-2.109 c0-0.826,0.627-1.596,1.51-1.596c0.04,0,0.078,0.005,0.116,0.007C16.472,3.904,14.34,3.009,12,3.009 c-3.141,0-5.904,1.612-7.512,4.052c0.211,0.007,0.41,0.011,0.579,0.011c0.94,0,2.396-0.114,2.396-0.114 C7.947,6.93,8.004,7.642,7.52,7.699c0,0-0.487,0.057-1.029,0.085l3.274,9.739l1.968-5.901l-1.401-3.838 C9.848,7.756,9.389,7.699,9.389,7.699C8.904,7.67,8.961,6.93,9.446,6.958c0,0,1.484,0.114,2.368,0.114 c0.94,0,2.397-0.114,2.397-0.114c0.485-0.028,0.542,0.684,0.057,0.741c0,0-0.488,0.057-1.029,0.085l3.249,9.665l0.897-2.996 C17.841,13.284,18.069,12.316,18.069,11.546z M19.889,7.686c0.039,0.286,0.06,0.593,0.06,0.924c0,0.912-0.171,1.938-0.684,3.22 l-2.746,7.94c2.673-1.558,4.47-4.454,4.47-7.771C20.991,10.436,20.591,8.967,19.889,7.686z M12,22C6.486,22,2,17.514,2,12 C2,6.486,6.486,2,12,2c5.514,0,10,4.486,10,10C22,17.514,17.514,22,12,22z\"><\/path><\/svg><span class=\"wp-block-social-link-label screen-reader-text\">WordPress<\/span><\/a><\/li>\n\n<li style=\"color: #ffffff; \" class=\"wp-social-link wp-social-link-mail  wp-block-social-link\"><a rel=\"noopener nofollow\" target=\"_blank\" href=\"mailto:paulchapman@uk.ibm.com\" class=\"wp-block-social-link-anchor\"><svg width=\"24\" height=\"24\" viewBox=\"0 0 24 24\" version=\"1.1\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" aria-hidden=\"true\" focusable=\"false\"><path d=\"M19,5H5c-1.1,0-2,.9-2,2v10c0,1.1.9,2,2,2h14c1.1,0,2-.9,2-2V7c0-1.1-.9-2-2-2zm.5,12c0,.3-.2.5-.5.5H5c-.3,0-.5-.2-.5-.5V9.8l7.5,5.6,7.5-5.6V17zm0-9.1L12,13.6,4.5,7.9V7c0-.3.2-.5.5-.5h14c.3,0,.5.2.5.5v.9z\"><\/path><\/svg><span class=\"wp-block-social-link-label screen-reader-text\">Mail<\/span><\/a><\/li>\n\n<li style=\"color: #ffffff; \" class=\"wp-social-link wp-social-link-youtube  wp-block-social-link\"><a rel=\"noopener nofollow\" target=\"_blank\" href=\"https:\/\/www.youtube.com\/@paulchapman1280\/videos\" class=\"wp-block-social-link-anchor\"><svg width=\"24\" height=\"24\" viewBox=\"0 0 24 24\" version=\"1.1\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" aria-hidden=\"true\" focusable=\"false\"><path d=\"M21.8,8.001c0,0-0.195-1.378-0.795-1.985c-0.76-0.797-1.613-0.801-2.004-0.847c-2.799-0.202-6.997-0.202-6.997-0.202 h-0.009c0,0-4.198,0-6.997,0.202C4.608,5.216,3.756,5.22,2.995,6.016C2.395,6.623,2.2,8.001,2.2,8.001S2,9.62,2,11.238v1.517 c0,1.618,0.2,3.237,0.2,3.237s0.195,1.378,0.795,1.985c0.761,0.797,1.76,0.771,2.205,0.855c1.6,0.153,6.8,0.201,6.8,0.201 s4.203-0.006,7.001-0.209c0.391-0.047,1.243-0.051,2.004-0.847c0.6-0.607,0.795-1.985,0.795-1.985s0.2-1.618,0.2-3.237v-1.517 C22,9.62,21.8,8.001,21.8,8.001z M9.935,14.594l-0.001-5.62l5.404,2.82L9.935,14.594z\"><\/path><\/svg><span class=\"wp-block-social-link-label screen-reader-text\">YouTube<\/span><\/a><\/li>\n\n<li style=\"color: #ffffff; \" class=\"wp-social-link wp-social-link-linkedin  wp-block-social-link\"><a rel=\"noopener nofollow\" target=\"_blank\" href=\"https:\/\/www.linkedin.com\/in\/chapmanp\/\" class=\"wp-block-social-link-anchor\"><svg width=\"24\" height=\"24\" viewBox=\"0 0 24 24\" version=\"1.1\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" aria-hidden=\"true\" focusable=\"false\"><path d=\"M19.7,3H4.3C3.582,3,3,3.582,3,4.3v15.4C3,20.418,3.582,21,4.3,21h15.4c0.718,0,1.3-0.582,1.3-1.3V4.3 C21,3.582,20.418,3,19.7,3z M8.339,18.338H5.667v-8.59h2.672V18.338z M7.004,8.574c-0.857,0-1.549-0.694-1.549-1.548 c0-0.855,0.691-1.548,1.549-1.548c0.854,0,1.547,0.694,1.547,1.548C8.551,7.881,7.858,8.574,7.004,8.574z M18.339,18.338h-2.669 v-4.177c0-0.996-0.017-2.278-1.387-2.278c-1.389,0-1.601,1.086-1.601,2.206v4.249h-2.667v-8.59h2.559v1.174h0.037 c0.356-0.675,1.227-1.387,2.526-1.387c2.703,0,3.203,1.779,3.203,4.092V18.338z\"><\/path><\/svg><span class=\"wp-block-social-link-label screen-reader-text\">LinkedIn<\/span><\/a><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Credit:<\/h2>\n\n\n\n<p>Errors are my own, credit to Bill &amp; TechXchange 2024.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/Bill-Starke-profile.jpg\" alt=\"\" class=\"wp-image-1691\" width=\"125\" height=\"125\" srcset=\"https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/Bill-Starke-profile.jpg 500w, https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/Bill-Starke-profile-300x300.jpg 300w, https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/Bill-Starke-profile-150x150.jpg 150w\" sizes=\"auto, (max-width: 125px) 100vw, 125px\" \/><\/figure>\n\n\n\n<p><a href=\"https:\/\/www.linkedin.com\/in\/bill-starke-3951814a\/\" target=\"_blank\" rel=\"noreferrer noopener\">William Starke<\/a>, IBM Distinguished Engineer and POWER Processor Chief Architect<\/p>\n\n\n\n<p><a href=\"https:\/\/reg.tools.ibm.com\/flow\/ibm\/techxchange24\/sessioncatalog\/page\/sessioncatalog?search=3043&amp;tab.sessioncatalogtabs=option_1601178495160\" target=\"_blank\" rel=\"noreferrer noopener\">IBM Power&#8217;s Differentiated Memory Roadmap<\/a><\/p>\n\n\n\n<p>IBM TechXchange 2024<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"574\" src=\"https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/3043-1024x574.jpg\" alt=\"\" class=\"wp-image-1690\" srcset=\"https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/3043-1024x574.jpg 1024w, https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/3043-300x168.jpg 300w, https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/3043-768x431.jpg 768w, https:\/\/nas01.tallpaul.net\/wordpress\/wp-content\/uploads\/2024\/11\/3043.jpg 1396w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p>This session explores the historical importance of Power&#8217;s memory architecture, reviews recent developments in Power&#8217;s memory roadmap, and highlights the strengths of Power&#8217;s memory architecture going forward versus developments in industry memory architectures.<\/p>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Explore how IBM Power&#8217;s innovative memory architecture is reshaping enterprise computing with 4x bandwidth, superior reliability, and future-proof design.<\/p>\n","protected":false},"author":1,"featured_media":1692,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3,6],"tags":[],"class_list":["post-1689","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ibm","category-power-systems"],"_links":{"self":[{"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/posts\/1689","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/comments?post=1689"}],"version-history":[{"count":0,"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/posts\/1689\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/media\/1692"}],"wp:attachment":[{"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/media?parent=1689"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/categories?post=1689"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/nas01.tallpaul.net\/wordpress\/wp-json\/wp\/v2\/tags?post=1689"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}